The present invention relates to static random access memories (“SRAMs”), and more particularly to arrays of SRAMs with column redundancy decoded onto a data-bus in a manner that allows for power savings during read cycles.
A basic SRAM cell includes a balanced pair of cross-coupled inverters storing a single data bit with a high at the output of one inverter and a low at the output of the other inverter. A pair of pass gates selectively connects the complementary outputs of the cross-coupled inverters to a corresponding complementary pair of bit lines. A word line connected to the pass gates selects the cell, connecting the cell contents to the corresponding complementary pair of bit lines.
SRAM cells are arranged in an SRAM array. Wordlines run in a direction of rows across an SRAM array. Bitlines run in a direction of columns across the SRAM array. Typically, one wordline is connected to each cell of a row of cells in the SRAM array. Typically, two bitlines carrying complementary signals are connected to each cell in a column of cells in the SRAM array. One of the complementary bitlines carries a “true” signal, representing the actual state of a bit signal, and the other bitline carries a “complementary” signal representing an inverted version of the bit signal.
A N-by-M SRAM array is organized as N rows of wordlines by M columns of bit line pairs. Accessing a K bit single word from the array entails driving one of the N word lines. During a read operation, each cell on the selected word line couples its contents to its corresponding bit line pair through the pass gates. Each cell on a selected column line may be coupled to a simple sense amplifier (“sense amp”). Since the bitline pair is typically precharged to some common voltage, initially, the internal low voltage rises until one of the bitline pairs drops sufficiently to develop a small difference signal on the bit line pair and the SA is triggered by a set signal to drive the BL to the desired state. The set signal controls one or more BLs.
SRAM macros are generally accessed using addresses. These addresses are employed to activate certain wordlines, which allow conductivity between activated or deactivated cells within subarrays and bitlines coupled thereto. Conventional decoders typically include an initial decode stage (or “predecode” state), as well as a final decode stage where the decoded addresses are used to activate selected wordlines to generate date from the memory macro.
Conventional SRAM arrays contain a greater number of BLs than the number of bits on the data bus they are connected to. Therefore, the BLs are decoded onto the data bus based on the address. Essentially only certain BLs are needed when accessing the data bus and the other BLs are not used.
Conventionally, BLs that are not decoded onto the data bus are still activated even though they are not used. The unused but activated BLs still consume power. A solution to this problem is to reduce the power consumption by decoding the address and only activating the SAs of the BLs which will be decoded onto the data bus. Therefore, if the data bus is one quarter the size of the number of BLs, only one quarter of the BLs will be activated when the data bus is accessed.
However, this approach does not work when the SRAM array contains column steering redundancy. Column steering redundancy allows for a column to be replaced by shifting all columns higher than the failing column down by one spot on the address and shifting in a redundant column to the position of the highest column. Traditional power saving with decoding of the BLs does not work when column steering redundancy is activated because it cannot account for the shift of the columns and not all proper BLs would be activated when the data bus is activated.